I always wonder where will x86 be in 10 or 20 years time. As data paths widen for SIMD, how many can they possibly cram even more generations of wider and wider groups of instruction with different opcodes and characteristics.

How will this be better than RISC V?

Who do you expect to answer? It's a tiny future product announcement, it neither exists, nor is it a Show HN from someone involved

a man can dream

Isn't this basically a GPU?

> This requires moving beyond the notion of shared mutable memory and linear instruction sequences.

Yep, and they're probably simulating/emulating their CPU design on GPUs already.

TL;DR: it's basically Niagara/GreenArrays/etc again.

Not sure why this one will succeed where its forebears didn't.

Have you seen the new CPU architecture? It's on Mill. It's literally on Transputer. It's on Rock with Sun. It's literally on AMULET. You can probably find it on Itanium. Dude it's on Tesla. It's a CDC STAR original. It's on E1. You can program it on E1. You can go to E1 and program it. Get onto E1 right now. Go to E1. Dive into E1. You can E1 it. It's on E1. E1 has it for you. E1 has it for you.

In all seriousness congratulations on finding $30 million to launder and lose immediately. Hope your Porsche runs good.

let's re-do the OS too. we only need about 10 syscalls. authorization is totally backwards (look how android runs a user per process).

Was about time we had another Transmeta.

Bet you they will turn into yet another ML accelerator company within the year.