Continuing the well established trend of making bold claims about physical dimensions that have nothing to do with any of the structures in the chip, and the name scales better than the tech.

What they actually deliver is a "nanostack architecture" built with ~5nm features that according to them is comparable to a hypothetical real sub-1nm chip.

It's an impressive achievement nonetheless but it looks like the industry has a few too many marketers.

For silicon, the gate length of a FET has a lower limit somewhere between 10 nm and 15 nm.

The current CMOS manufacturing processes have not reached the limit yet. For making smaller transistors, a transition to other semiconductor materials will be necessary.

The vertical thicknesses of various layers may be of only a few nanometers or even of a fraction of a nanometer, but that does not matter directly for the circuit density.

The supposed node size refers to horizontal dimensions, not to vertical dimensions.

Vertical dimensions of around 1 nanometer or less could be achieved already many decades ago, because they depend on growth speed and on time, not on lithography, like the horizontal dimensions.

The industry should have stopped decades ago to talk about the "size" but they should have characterized a CMOS process by its density, e.g. in logic gates per square mm.

However, an actual concrete number would be disliked by marketing, because they could no longer claim that their "1 nm" process is better than the "2 nm" process of another vendor, if their density is not really better.

It describes density measure where you can compare it to planar transistors from the 28-nanometer (28 nm) node around 2010 to 2011 and before. A "0.7 nm" node has equivalent transistor density as if we could have shrunk standard flat transistor node down to 0.7 nanometers.

mass per volume is one example.

> Historically, "node" sizes (like 28nm or 7nm) directly correlated to the physical length of a transistor's gate. Today, names like 3nm or 2nm reflect a marketing generation. The actual transistors are significantly larger than these nanometer labels, meaning density varies between companies

> Research organizations like IEEE have proposed new metrics, such as transistors per cubic millimeter (MTr/mm^3), to accurately map future 3D scaling. However, commercial chip foundries resist this change because it would make it harder to calculate commercial yields and thermal density limits using standard industry formulas.

https://share.google/aimode/Z5BqUjlZWFNphm6Z6

I know they won't go for an anything that makes as much sense as 5nm3, so I vote for "1nm hyper space"

The intended meaning of "0.7 nm" is that if you compare the transistor density per area of a "0.7 nm" manufacturing process with that of a "350 nm" process (like used for some Pentium II CPUs, at a time when "350 nm" was a real length), the ratio between the transistor densities is (350 nm / 0.7 nm)^2 = 500^2 = 250,000.

Comparing with the number of transistors of a Pentium II, a 0.7 nm CPU should be able to contain about 5000 billion transistors. This is consistent with the fact that the latest 3 nm NVIDIA Rubin GPU has 336 billion transistors and a 0.7 nm circuit must have a density around 16 times greater than a 3 nm circuit.

However, for many of the modern node names used by some companies even this computation is not really true, because marketing may have chosen an arbitrary name that is smaller than for the last process of the main competitor.

For now, IBM has not provided any kind of information that could prove their claim that their new CMOS process has the transistor density corresponding to "0.7 nm" (i.e. 16 times greater than the TSMC "3 nm" CMOS process).

Different companies measure it differently too. This was a while ago, but I remember reading that Intel 10nm was more or less close to TSMC 7nm. I'm sure this is still true to varying degrees.

Never heard of this, care to elaborate?

The money-making parts of IBM are: legacy software and hardware (declining), consulting (low margin, low leverage), enterprise software (mostly redhat, not really growing). It's hard to explain how IBM research is accretive to any of that.

They are also betting on quantum computing to become commercially relevant.

Broadly speaking yes, this is the business model. IBM has been at this for many years with technology transfers, licensing agreements, support and other arrangements. Rapidus, Samsung, GlobalFoundries, ST, SMIC, AMD, etc. have all used IBM R&D work at various times for various nodes and products.

The cutting edge of semiconductors is a writhing mass of copulating tapeworms, and IBM lives deep inside that ball. For IBM, what this means is that when you buy one of the ASML machines to make products with this process, you'll pay IBM for the knowledge and support to actually get it working, or give them a cut, or something else, TBD, as circumstances warrant.

1. The OP has nothing to do with quantum computers.

2. Quantum computing deals in coherent quantum states: associated with N qubits there are 2^N complex amplitudes. You can measure by sampling the square-magnitude of the complex amplitude which turns it into a Probability Distribution. Quantum computing "gates" cause interference in the complex amplitude of entangled qubits cancelling out incorrect results, such that if you maintain coherence for long enough and sample the final state and measure the probability distribution, you get a computationally useful result. The key challenge in quantum computing is extending the coherence time of a larger and larger number of qubits, which is why you hear so much about quantum error correction. Recent results from Google showed a scaling law for "surface codes" using multiple qubits to create an error-corrected topological qubit with extended lifetime. There is no telling how far this scaling law will go, but as long as Gil Kalai is in the next room, it is unlikely there will be actual useful quantum computation for a while.

Is there a limit to how small things can go? A single atom?

Is there a physical/molecular limit to Moore's Law?

Once you make the gate of a transistor small/thin enough, quantum effects take over. Electrons will randomly teleport into and through the gate causing the transistor to conduct when it shouldn't. I don't have numbers to hand, but it's on the order of a few atoms wide. There's really nothing that can be done about it either, as far as we know. Electrons just aren't physical objects at this scale, you can't simply exclude them from any given volume of space. The electron wave function will simply just appear wherever it wants (within the electron probability cloud). The only way to stop it is to make your insulating junction thicker than the probability cloud.

I don't know which is more ridiculous, the fact that reality works like this, or, that a species of apes was able to figure this out.

Even if there isn’t, the way it seems all based on the uneven flow of state over spacetime is deeply fascinating for someone who studies computing.

... inside a silicon crystal.

You can keep the electrons into as small a volume as you want, but you need something there forcing them, and doped silicon will only force them so much.

In fact, those transistors are smaller than what a silicon crystal can do, and the electrons are only held there because they are made of more materials than only silicon.

https://en.wikipedia.org/wiki/Landauer%27s_principle

Yes, single-atom manipulation has already been demonstrated:

* https://en.wikipedia.org/wiki/IBM_(atoms)

Can you make transistors using that technique? Can you smaller?

You also have quantum computing, which I think can/does use subatomic particles? Not sure about that one

Another type of quantum computer uses qubits consisting of "quantum circuits" which are actually huge macroscopic constructions (> 1mm).

Wait, what? How does this work in principle for storage? You can store electrons but you're saying you can store photons too?

>We got pretty damn close in the vacuum tube era

Uh, what?

There's only so many fundamental interactions in the Universe. Computing requires you to be able to distinguish two states and our current methodology is built around some sort of black box three input machine that can output either state, a switch.

That switch is the part that cannot be scaled down infinitely. The reality we are familiar with doesn't exist at atomic scales. "Things" don't even have properly defined boundaries at a certain level, and thermal noise is a huge issue.

IMO a much more direct limiter of our current computing capability is lack of manufacturing ability, and heat. We were lucky that transistors were so amenable to lithography as a concept, that they work so well in 2D and as a surface feature, as that is what drove our advances the past 100 years and enabled computing to be such a normal thing. The combination of a "Solid state" effect, the electric force having very convenient properties, and lithography being so amenable to scaling things in various directions is how we got here.

But lithography doesn't scale into 3D. We've been hacking around that by doing more layers but that scales awfully, has very strict limitations, and makes the heat problem infinitely worse, to the point of making it impossible to work around.

If we could assemble things atom by atom exactly how we want, we could vastly improve our theory and practice, and build really intricate processor chunks with effective cooling channels or something, and computing would scale so much more. Maybe. Maybe some other problem would suddenly start dominating in that world.

Biology literally is nanotechnology, but it takes massive tradeoffs in exchange. It might never be possible to manufacture, at scale, stuff atom by atom. The Universe doesn't promise us infinite progress in technology. Quite the opposite.

I'm guessing that this is the technology that is developed by Cymer (ASML subsidiary) in California, correct? Is there competing technology? I know xLight is trying to make some inroads on their own version of this EUV tech. I have not heard about any progress though.

also, I was expecting to see cfets mentioned.

Why? What's their real size?

Not doubting you, just trying to understand and also trying to assess how exaggerated the marketing is.

Currently thrown around numbers mean the "equivalent performance/density" or something like that.

So many breakthroughs in hard drives, chips, transistor density, and other aspects of computing have come out of their labs.

Great to see them continuing to innovate.

But, yeah, usually they partner and license. Over the years, they've spun off more and more of their hardware businesses.

I wonder why isn't this more common.

https://www.ibm.com/products/z/telum

Per IBM: "IBM Research at Albany [...] includes more than 100,000 square feet of semiconductor fabrication space"

I guess that is technically a R&D fab not a production one, but they definitely have in house fabrication capability

My understanding is that ASML's acquisition of Cymer in California (the actual EUV light source technology) in 2014 was only permitted under a strict technology sharing and export agreement with the US government. And that the technology development and production had to remain within the US.

The USA CHIPS Act and NY State have provided $100 billion+ in funding with the expectation that ASML's core R&D and "prototyping" like this will be done in the US in partnership with US companies (like IBM).

Otherwise, that chip tech sounds really awesome - at least for the future!

https://en.wikipedia.org/wiki/Angstrom

However, version 5 of the standard already deprecates that code point and has it normalized into the code for the Swedish letter U+00C5 Å `latin capital letter a with ring above`

(In the same way that meter jumps three orders of magnitude to kilometer[1], or millions to billions to trillions, etc.)

[1] Technically there are intermediate SI units between meter and km but nobody uses them. There are not intermediate SI units between the tiny ones.

We have centimeter (10 mm) then decimeter (100mm) then meter (1000mm). Then we jump to thousand again (kilometer).

Does anyone actually use those? I think I would throw up a little in my mouth if I saw either of those on a mechanical drawing.

1 Å = 100 pm. 1 pm = 0.01 Å.

1 angstrom = 0.1 nanometers, 100 picometers

1 nanometer = 10 angstroms, 1000 picometers